MC68HC16Z1 Datasheet, PDF (270/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Name
—
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
TO
PAOV
PAI
Table 11-2 GPT Interrupt Sources
Source
Number
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Source
Adjusted channel
Input capture 1
Input capture 2
Input capture 3
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Input capture 4/output compare 5
Timer overflow
Pulse accumulator overflow
Pulse accumulator input
Vector
Number
IVBA : 0000
IVBA : 0001
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
The CPU16 recognizes only interrupt request signals of a priority greater than the con-
dition code register interrupt priority (IP) mask value. When the CPU acknowledges an
interrupt request, the priority of the acknowledged request is written to the IP mask and
driven out on the IMB address lines.
When the IP mask value driven out on the address lines is the same as the IRL value,
the GPT contends for arbitration priority. GPT arbitration priority is determined by the
value of IARB[3:0] in GPTMCR. Each MCU module that can make interrupt requests
must be assigned a non-zero IARB value to implement an arbitration scheme. Arbitra-
tion is performed by serial assertion of IARB[3:0] bit values.
When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge
cycle by placing an interrupt vector number on the data bus. The vector number is
used to calculate displacement into the CPU16 exception vector table. Vector num-
bers are formed by concatenating the value in ICR IVBA[3:0] with a 4-bit value sup-
plied by the GPT when an interrupt request is made. Hardware prevents the vector
number from changing while it is being driven out on the IMB. Vector number assign-
ment is shown in Table 11-2.
At reset, IVBA[3:0] is initialized to $0. To enable interrupt-driven timer operation, the
upper nibble of a user-defined vector number ($40 – $FF) must be written to IVBA, and
interrupt handler routines must be located at the addresses pointed to by the corre-
sponding vector.
NOTE
IVBA[3:0] must be written before GPT interrupts are enabled, or the
GPT could supply a vector number ($00 to $0F) that corresponds to
an assigned or reserved exception vector.
The internal GPT interrupt priority hierarchy is shown in Table 11-2. The lower the in-
terrupt source number, the higher the priority. A single GPT interrupt source can be
given priority over all other GPT interrupt sources by assigning the priority adjust field
(IPA[3:0]) in the ICR a value equal to its source number.
11-6
GENERAL-PURPOSE TIMER
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M68HC16 Z SERIES
USER’S MANUAL