MC68HC16Z1 Datasheet, PDF (64/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
4.2.5 Condition Code Register
The 16-bit condition code register is composed of two functional blocks. The eight
MSB, which correspond to the CCR on the M68HC11, contain the low-power stop con-
trol bit and processor status flags. The eight LSB contain the interrupt priority field, the
DSP saturation mode control bit, and the program counter address extension field.
Figure 4-2 shows the condition code register. Detailed descriptions of each status in-
dicator and field in the register follow the figure.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
MV
H
EV
N
Z
V
C
IP[2:0]
SM
PK[3:0]
Figure 4-2 Condition Code Register
S — STOP Enable
0 = Stop clock when LPSTOP instruction is executed.
1 = Perform NOP when LPSTOP instruction is executed.
MV — Accumulator M overflow flag
MV is set when an overflow into AM35 has occurred.
H — Half Carry Flag
H is set when a carry from A3 or B3 occurs during BCD addition.
EV — Accumulator M Extension Overflow Flag
EV is set when an overflow into AM31 has occurred.
N — Negative Flag
N is set under the following conditions:
• When the MSB is set in the operand of a read operation.
• When the MSB is set in the result of a logic or arithmetic operation.
Z — Zero Flag
Z is set under the following conditions:
• When all bits are zero in the operand of a read operation.
• When all bits are zero in the result of a logic or arithmetic operation.
V — Overflow Flag
V is set when a two’s complement overflow occurs as the result of an operation.
C — Carry Flag
C is set when a carry or borrow occurs during an arithmetic operation. This flag is also
used during shift and rotate to facilitate multiple word operations.
IP[2:0] — Interrupt Priority Field
The priority value in this field (0 to 7) is used to mask interrupts.
CENTRAL PROCESSOR UNIT
M68HC16 Z SERIES
4-4
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