MC68HC16Z1 Datasheet, PDF (199/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
INITIAL
SAMPLE
TIME
1
FINAL
TRANSFER SAMPLE
TIME
TIME
(2 ADC CLOCKS)
RESOLUTION TIME
TRANSFER CONVERSION TO
RESULT REGISTER AND SET
CCF
16
6 CYCLES
SAMPLE AND TRANSFER
PERIOD
2
CYCLES
SAR9
1
1
1
1
1
1
1
1
1
1
CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE
SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SAR1 SAR0 EOC
SUCCESSIVE APPROXIMATION
END
SEQUENCE
CH 1
CH 2
CH 3
CH 4
SCF FLAG SET HERE AND SEQUENCE
ENDS IF IN THE 4-CHANNEL MODE
CH 5
CH 6
CH 7
CH 8
SCF FLAG SET HERE AND SEQUENCE
ENDS IF IN THE 8-CHANNEL MODE
Figure 8-3 10-Bit Conversion Timing
16 ADC 10-BIT TIM
8.7.7 Successive Approximation Register
The successive approximation register (SAR) accumulates the result of each conver-
sion one bit at a time, starting with the most significant bit.
At the start of the resolution period, the MSB of the SAR is set, and all less significant
bits are cleared. Depending on the result of the first comparison, the MSB is either left
set or cleared. Each successive bit is set or left cleared in descending order until all
eight or ten bits have been resolved.
When conversion is complete, the content of the SAR is transferred to the appropriate
result register. Refer to APPENDIX D REGISTER SUMMARY for register mapping
and configuration.
8.7.8 Result Registers
Result registers are used to store data after conversion is complete. The registers can
be accessed from the IMB under ABIU control. Each register can be read from three
different addresses in the ADC memory map. The format of the result data depends
on the address from which it is read. Table 8-9 shows the three types of formats.
M68HC16 Z SERIES
USER’S MANUAL
ANALOG-TO-DIGITAL CONVERTER
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8-13