MC68HC16Z1 Datasheet, PDF (155/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table 5-18 Reset Source Summary
Type
External
Power up
Software watchdog
HALT
Loss of clock
Test
Source
External
EBI
Monitor
Monitor
Clock
Test
Timing
Synch
Asynch
Asynch
Asynch
Synch
Synch
Cause
RESET pin
V_DD
Time out
Internal HALT assertion
(e.g. double bus fault)
Loss of reference
Test mode
Reset Lines Asserted by
Controller
MSTRST CLKRST EXTRST
MSTRST CLKRST EXTRST
MSTRST CLKRST EXTRST
MSTRST CLKRST EXTRST
MSTRST CLKRST EXTRST
MSTRST
—
EXTRST
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in Figure 5-18.
5.7.3 Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 5-19 is a summary of reset mode selection options.
Table 5-19 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
DATA0
CSBOOT 16-Bit
CSBOOT 8-Bit
CS0
DATA1
CS1
CS2
BR
BG
BGACK
CS3
FC0
DATA2
CS4
FC1
CS5
FC2
DATA3
DATA4
DATA5
DATA6
DATA7
CS6
CS[7:6]
CS[8:6]
CS[9:6]
CS[10:6]
ADDR19
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
DATA8
DSACK[1:0],
AVEC, DS, AS,
SIZ[1:0]
PORTE
DATA9
IRQ[7:1]
MODCLK
PORTF
DATA11
Normal Operation¹
Reserved
MODCLK
VCO = System Clock
EXTAL = System Clock
BKPT
Background Mode Disabled
Background Mode Enabled
NOTES:
1. DATA11 must remain high during reset to ensure normal operation.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
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