MC68HC16Z1 Datasheet, PDF (49/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table 3-5 M68HC16 Z-Series Signal Function
Mnemonic
ADDR[19:0]
AN[7:0]
AS
AVEC
BERR
BG
BGACK
BKPT
BR
CLKOUT
CS[10:0]
CSBOOT
DATA[15:0]
DS
DSACK[1:0]
DSI, DSO,
DSCLK
EXTAL, XTAL
FC[2:0]
FREEZE
HALT
IRQ[7:1]
IPIPE[1:0]
MISO
MISO¹
MODCLK
MOSI
MOSI¹
PADA[7:0]
PAI
PCLK
PC[6:0]
PCS[3:0]
PE[7:0]
Signal Name
Address Bus
ADC Analog Input
Function
20-bit address bus used by CPU16
Inputs to ADC multiplexer
Address Strobe
Autovector
Bus Error
Indicates that a valid address is on the address bus
Requests an automatic vector during interrupt acknowledge
Indicates that a bus error has occurred
Bus Grant
Indicates that the MCU has relinquished the bus
Bus Grant
Acknowledge
Breakpoint
Indicates that an external device has assumed bus mastership
Signals a hardware breakpoint to the CPU
Bus Request
System Clockout
Chip-Selects
Indicates that an external device requires bus mastership
System clock output
Select external devices at programmed addresses
Boot Chip Select
Data Bus
Data Strobe
Chip select for external boot start-up ROM
16-bit data bus
During a read cycle, indicates that an external device should
place valid data on the data bus. During a write cycle, indicates
that valid data is on the data bus.
Data and Size
Acknowledge
Provide asynchronous data transfers and dynamic bus sizing
Development Serial In, _{Serial I/O and clock for background debug mode}
Out, Clock
Crystal Oscillator
Function Codes
Connections for clock synthesizer circuit reference a crystal or
an external oscillator can be used
Identify processor state and current address space
Freeze
Halt
Interrupt Request Level
Indicates that the CPU has entered background mode
Suspend external bus activity
Provides an interrupt priority level to the CPU
Instruction Pipeline
Master In Slave Out
Indicate instruction pipeline activity
Serial input to QSPI in master mode; serial output from QSPI in
slave mode
Master In Slave Out
Serial input to SPI in master mode; serial output from SPI in
slave mode
Clock Mode Select
Master Out Slave In
Selects the source and type of system clock
Serial output from QSPI in master mode; serial input to QSPI in
slave mode
Master Out Slave In
Port ADA
Serial output from SPI in master mode; serial input to SPI in
slave mode
ADC digital input port signals
Pulse Accumulator Input
Auxiliary Timer Clock
Port C
Peripheral Chip Select
Port E
Input to the GPT pulse accumulator
GPT external clock input
Port C digital output port signals
QSPI peripheral chip-selects
Port E digital I/O port signals
M68HC16 Z SERIES
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