MC68HC16Z1 Datasheet, PDF (228/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table 9-3 Bits Per Transfer
BITS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits Per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. Writing a value to DTL[7:0] in SPCR1 specifies a delay period. The
DT bit in each command RAM byte determines whether the standard delay period (DT
= 0) or the user-specified delay period (DT = 1) is used. The following expression is
used to calculate the delay:
Delay after Transfer = ³----²-----^×----^D-_f--_s--^T_y---_s^L----^[-⁷----^:-⁰----^] if DT = 1
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/f_sys.
Standard Delay after Transfer = --¹---⁷--- if DT = 0
f_sys
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased proportion-
ately.
9-18
QUEUED SERIAL MODULE
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M68HC16 Z SERIES
USER’S MANUAL