MC68HC16Z1 Datasheet, PDF (171/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Port size determines the way in which bus transfers to an external address are allo-
cated. Port size of eight bits or sixteen bits can be selected when a pin is assigned as
a chip-select. Port size and transfer size affect how the chip-select signal is asserted.
Refer to 5.9.1.3 Chip-Select Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a correspond-
ing data bus pin. The data bus pins have weak internal pull-up drivers, but can be held
low by external devices. Refer to 5.7.3.1 Data Bus Mode Selection for more informa-
tion. Either 16-bit chip-select function (%11) or alternate function (%01) can be select-
ed during reset. All pins except the boot ROM select pin (CSBOOT) are disabled out
of reset. There are twelve chip-select functions and only eight associated data bus
pins. There is not a one-to-one correspondence. Refer to 5.9.4 Chip-Select Reset
Operation for more detailed information.
The CSBOOT signal is enabled out of reset. The state of the DATA0 line during reset
determines what port width CSBOOT uses. If DATA0 is held high (either by the weak
internal pull-up driver or by an external pull-up device), 16-bit port size is selected. If
DATA0 is held low, 8-bit port size is selected.
A pin programmed as a discrete output drives an external signal to the value specified
in the port C register. No discrete output function is available on CSBOOT, BR, BG, or
BGACK. ADDR23 provides the ECLK output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select
logic still functions and can be used to generate DSACK or AVEC internally on an ad-
dress and control signal match.
5.9.1.2 Chip-Select Base Address Registers
Each chip-select has an associated base address register. A base address is the low-
est address in the block of addresses enabled by a chip-select. Block size is the extent
of the address block above the base address. Block size is determined by the value
contained in BLKSZ[2:0]. Multiple chip-selects assigned to the same block of address-
es must have the same number of wait states.
BLKSZ[2:0] determines which bits in the base address field are compared to corre-
sponding bits on the address bus during an access. Provided other constraints deter-
mined by option register fields are also satisfied, when a match occurs, the associated
chip-select signal is asserted. Table 5-24 shows BLKSZ[2:0] encoding.
Table 5-24 Block Size Encoding
BLKSZ[2:0]
000
001
010
011
Block Size
2 Kbytes
8 Kbytes
16 Kbytes
64 Kbytes
Address Lines Compared¹
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
100
128 Kbytes
101
256 Kbytes
110
512 Kbytes
111
512 Kbytes
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
NOTES:
1. ADDR[23:20] are the same logic level as ADDR19 during normal op-
eration.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
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