MC68HC16Z1 Datasheet, PDF (310/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table A-18 25.17-MHz AC Timing (Continued)
(V_DD and V_DDSYN = 5.0 Vdc ± 5%, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
30
30A
31
33
35
37
39
39A
46
46A
47A
Characteristic
CLKOUT Low to Data In Invalid (Fast Cycle Hold)⁷
CLKOUT Low to Data In High Impedance⁷
DSACK[1:0] Asserted to Data In Valid⁹
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted¹⁰
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
Symbol Min
t_CLDI
8
t_CLDH
—
t_DADI
—
t_CLBAN
—
t_BRAGA
1
t_GAGN
1
t_GH
2
t_GA
1
t_RWA
90
t_RWAS
55
t_AIST
5
Max
—
60
35
19
—
2
—
—
—
—
—
Unit
ns
ns
ns
ns
t_cyc
t_cyc
t_cyc
t_cyc
ns
ns
ns
47B Asynchronous Input Hold Time
48 DSACK[1:0] Asserted to BERR, HALT Asserted¹¹
t_AIHT
10
t_DABA
—
—
ns
27
ns
53 Data Out Hold from Clock High
t_DOCH
0
—
ns
54 Clock High to Data Out High Impedance
t_CHDH
—
23
ns
55 R/W Asserted to Data Bus Impedance Change
t_RADC
25
—
ns
70 Clock Low to Data Bus Driven (Show Cycle)
t_SCLDD
0
19
ns
71 Data Setup Time to Clock Low (Show Cycle)
t_SCLDS
8
—
ns
72 Data Hold from Clock Low (Show Cycle)
t_SCLDH
8
—
ns
73 BKPT Input Setup Time
t_BKST
10
—
ns
74 BKPT Input Hold Time
t_BKHT
10
—
ns
75 Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
t_MSS
20
—
t_cyc
76 Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
77 RESET Assertion Time¹²
78 RESET Rise Time¹³
100 CLKOUT High to Phase 1 Asserted¹⁴
101 CLKOUT High to Phase 2 Asserted¹⁴
102 Phase 1 Valid to AS or DS Asserted¹⁴
103 Phase 2 Valid to AS or DS Asserted¹⁴
104 AS or DS Valid to Phase 1 Negated¹⁴
105 AS or DS Negated to Phase 2 Negated¹⁴
t_MSH
0
t_RSTA
4
t_RSTR
—
t_CHP1A
3
t_CHP2A
3
t_P1VSA
9
t_P2VSN
9
t_SAP1N
9
t_SNP2N
9
—
ns
—
t_cyc
10
t_cyc
34
ns
34
ns
—
ns
—
ns
—
ns
—
ns
NOTES:
1. All AC timing is shown with respect to V_IH/V_IL levels unless otherwise noted.
2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable t_Xcyc period is reduced when the duty cycle of the external clock varies. The relationship between
external clock input duty cycle and minimum t_Xcyc is expressed:
Minimum t_Xcyc period = minimum t_XCHL / (50% – external clock input duty cycle tolerance).
A-26
ELECTRICAL CHARACTERISTICS
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