MC68HC16Z1 Datasheet, PDF (156/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
5.7.3.1 Data Bus Mode Selection
All data lines have weak internal pull-up devices. When pins are held high by the in-
ternal pull-ups, the MCU uses a default operating configuration. However, specific
lines can be held low externally during reset to achieve an alternate configuration.
NOTE
External bus loading can overcome the weak internal pull-up drivers
on data bus lines and hold pins low during reset.
Use an active device to hold data bus lines low. Data bus configuration logic must re-
lease the bus before the first bus cycle after reset to prevent conflict with external
memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is re-
leased. If external mode selection logic causes a conflict of this type, an isolation re-
sistor on the driven lines may be required. Figure 5-18 shows a recommended
method for conditioning the mode select signals.
DATA15
DATA8
DATA7
DATA0
V_DD
V_DD
V_DD
820 Ω
RESET
10 kΩ
10 kΩ
OUT1
OUT8
74HC244 OE
IN1
IN8
TIE INPUTS
HIGH OR LOW
AS NEEDED
OUT1
OUT8
74HC244 OE
IN1
IN8
TIE INPUTS
HIGH OR LOW
AS NEEDED
DS
R/W
DATA BUS SELECT CONDITIONING
Figure 5-18 Preferred Circuit for Data Bus Mode Select Conditioning
5-50
SYSTEM INTEGRATION MODULE
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M68HC16 Z SERIES
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