MC68HC16Z1 Datasheet, PDF (427/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
DT — Delay after Transfer
0 = Delay after transfer is 17 ÷ f_sys.
1 = SPCR1 DTL[7:0] specifies delay after transfer.
DSCK — PCS to SCK Delay
0 = PCS valid to SCK delay is one-half SCK.
1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.
PCS[3:0] — Peripheral Chip Select
Use peripheral chip-select bits to select one or more external devices for serial data
transfers. More than one peripheral chip select may be activated at a time, and more
than one peripheral chip can be connected to each PCS pin, provided proper fanout
is observed. PCS0 shares a pin with the slave select (SS) signal, which initiates slave
mode serial transfers. If SS is taken low when the QSPI is in master mode, a mode
fault occurs.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
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