MC68HC16Z1 Datasheet, PDF (279/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
10
INTERRUPT
REQUESTS
11
TMSK2
TFLG2
SYNCHRONIZER
EDGE
PAI
&
DETECT
DIGITAL FILTER
LOGIC
OVERFLOW
2:1
PACNT
MUX
8-BIT COUNTER
ENABLE
PACTL
PCLK
TCNT OVERFLOW
CAPTURE/COMPARE CLK
MUX
PRESCALER 512
INTERNAL
DATA BUS
Figure 11-5 Pulse Accumulator Block Diagram
16/32 PULSE ACC BLOCK
In event counting mode, the counter increments each time a selected transition of the
pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the sys-
tem clock divided by four.
In gated time accumulation mode a clock increments PACNT while the PAI pin is in
the active state. There are four possible clock sources.
Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator
flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse
accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has
rolled over from $FF to $00. This can be used to extend the range of the counter be-
yond eight bits.
M68HC16 Z SERIES
USER’S MANUAL
GENERAL-PURPOSE TIMER
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