MC68HC16Z1 Datasheet, PDF (397/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
D.3 Standby RAM Module
Table D-19 shows the SRAM address map.
Table D-19 SRAM Address Map
Address¹ 15
0
$YFFB00
RAM Module Configuration Register (RAMMCR)
$YFFB02
RAM Test Register (RAMTST)
$YFFB04
RAM Array Base Address Register High (RAMBAH)
$YFFB06
RAM Array Base Address Register Low (RAMBAL)
NOTES:
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.3.1 RAM Module Configuration Register
RAMMCR — RAM Module Configuration Register
15
11
9
8
STOP
0
0
0 RLCK 0
RASP[1:0]
RESET:
1
0
0
0
0
0
1
1
NOT USED
$YFFB00
0
STOP — Low-Power Stop Mode Enable
0 = SRAM operates normally.
1 = SRAM enters low-power stop mode.
This bit controls whether SRAM operates normally or enters low-power stop mode. In
low-power stop mode, the array retains its contents, but cannot be read or written. This
bit can be read or written at any time.
RLCK — RAM Base Address Lock
0 = SRAM base address registers can be written.
1 = SRAM base address registers are locked and cannot be modified.
RLCK defaults to zero on reset; it can be written once to a one, and may be read at
any time.
RASP[1:0] — RAM Array Space
The RASP field limits access to the SRAM array in microcontrollers that support sep-
arate user and supervisor operating modes. RASP1 has no effect because the CPU16
operates in supervisor mode only. This bit may be read or written at any time. Refer to
Table D-20.
Table D-20 SRAM Array Address Space Type
RASP[1:0]
X0
X1
Space
Program and data accesses
Program access only
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
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D-23