MC68HC16Z1 Datasheet, PDF (431/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
ILSPI[2:0] — Interrupt Level for SPI
ILSPI[2:0] determine the interrupt request levels of SPI interrupts. Program this field
to a value from $0 (interrupts disabled) through $7 (highest priority). If the interrupt-
request level programmed in this field matches the interrupt-request level pro-
grammed for one of the SCI interfaces and both request an interrupt simultaneously,
the SPI is given priority.
Bits [10:8] — Not Implemented
D.7.6 MCCI Pin Assignment Register
MPAR — MCCI Pin Assignment Register
15 14
13
12
11 10
9
8
NOT USED
RESET:
0
0
0
0
0
0
0
0
7
6
5
$YFFC08
4
3
2
1
0
MPA3
NOT
USED
MPA1
MPA0
0
0
0
The MPAR determines which of the SPI pins, with the exception of the SCK pin, are
actually used by the SPI submodule, and which pins are available for general-purpose
I/O. The state of SCK is determined by the SPI enable bit in SPCR1. Clearing a bit in
MPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the
pin to the SPI. Refer to Table D-39.
Table D-39 MPAR Pin Assignments
MPAR Field
MPAR Bit
Pin Function
MPA0
0
1
PMC0
MISO
MPA1
0
1
PMC1
MOSI
—¹
—
PMC2
SCK
MPA3
0
1
PMC3
SS
—¹
—
PMC4
RXDB
—¹
—
PMC5
TXDB
—¹
—
PMC6
RXDA
—¹
—
PMC7
TXDA
NOTES:
1. MPA[7:4], MPA2 are not implemented.
Bits [15:8], [7:4], 2 — Not Implemented
SPI pins designated by the MPAR as general-purpose I/O are controlled only by
MDDR and PORTMC. The SPI has no effect on these pins. The MPAR does not affect
the operation of the SCI submodule.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
D-57