MC68HC16Z1 Datasheet, PDF (101/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
4.14.1.1 IPIPE0/IPIPE1 Multiplexing
Six types of information are required to track pipeline activity. To generate the six state
signals, eight pipeline states are encoded and multiplexed into IPIPE0 and IPIPE1.
The multiplexed signals have two phases. State signals are active low. Table 4-6
shows the encoding scheme.
Phase
1
2
Table 4-6 IPIPE0/IPIPE1 Encoding
IPIPE1 State
0
0
1
1
0
0
1
1
IPIPE0 State
0
1
0
1
0
1
0
1
State Signal Name
START and FETCH
FETCH
START
NULL
INVALID
ADVANCE
EXCEPTION
NULL
IPIPE0 and IPIPE1 are timed so that a logic analyzer can capture all six pipeline state
signals and address, data, or control bus state in any single bus cycle. Refer to AP-
PENDIX A ELECTRICAL CHARACTERISTICS for specifications.
State signals can be latched asynchronously on the falling and rising edges of either
address strobe (AS) or data strobe (DS). They can also be latched synchronously us-
ing the microcontroller CLKOUT signal. Refer to the CPU16 Reference Manual
(CPU16RM/AD) for more information on the CLKOUT signal, state signals, and state
signal demux logic.
4.14.1.2 Combining Opcode Tracking with Other Capabilities
Pipeline state signals are useful during normal instruction execution and execution of
exception handlers. The signals provide a complete model of the pipeline up to the
point a breakpoint is acknowledged.
Breakpoints are acknowledged after an instruction has executed, when it is in pipeline
stage C. A breakpoint can initiate either exception processing or background debug
mode. IPIPE0/IPIPE1 are not usable when the CPU16 is in background debug mode.
4.14.2 Breakpoints
Breakpoints are set by assertion of the microcontroller BKPT pin. The CPU16 supports
breakpoints on any memory access. Acknowledged breakpoints can initiate either ex-
ception processing or background debug mode. After BDM has been enabled, the
CPU16 will enter BDM when the BKPT input is asserted.
• If BKPT assertion is synchronized with an instruction prefetch, the instruction is
tagged with the breakpoint when it enters the pipeline, and the breakpoint occurs
after the instruction executes.
• If BKPT assertion is synchronized with an operand fetch, breakpoint processing
occurs at the end of the instruction during which BKPT is latched.
M68HC16 Z SERIES
USER’S MANUAL
CENTRAL PROCESSING UNIT
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