MC68HC16Z1 Datasheet, PDF (135/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
The PIRQL field is compared to the CPU16 interrupt priority mask to determine wheth-
er the interrupt is recognized. Table 5-12 shows PIRQL[2:0] priority values. Because
of SIM hardware prioritization, a PIT interrupt is serviced before an external interrupt
request of the same priority. The periodic timer continues to run when the interrupt is
disabled.
Table 5-12 Periodic Interrupt Priority
PIRQL[2:0]
000
001
010
011
100
101
110
111
Priority Level
Periodic Interrupt Disabled
Interrupt priority level 1
Interrupt priority level 2
Interrupt priority level 3
Interrupt priority level 4
Interrupt priority level 5
Interrupt priority level 6
Interrupt priority level 7
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number is used to calculate the address
of the appropriate exception vector in the exception vector table. The reset value of
the PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.
5.4.8 Low-Power STOP Operation
When the CPU16 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSIM bit in the SYNCR, and the MCU enters low-power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power
stop.
During low-power stop mode, the clock input to the software watchdog timer is dis-
abled and the timer stops. The software watchdog begins to run again on the first rising
clock edge after low-power stop mode ends. The watchdog is not reset by low-power
stop mode. A service sequence must be performed to reset the timer.
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues
to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with
a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external
interrupt request, can bring the MCU out of the low-power stop mode if it has a higher
priority than the interrupt mask value stored in the clock control logic when low-power
stop mode is initiated. LPSTOP can be terminated by a reset.
5.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 5-10 shows a basic system with external memory and
peripherals.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
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