MC68HC16Z1 Datasheet, PDF (236/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
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Table 9-4 Serial Frame Formats
10-Bit Frames
Data
Parity/Control
7
—
7
1
8
—
11-Bit Frames
Data
Parity/Control
7
1
8
1
Stop
2
1
1
Stop
2
1
9.4.3.3 Baud Clock
The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI
control register 0 (SCCR0). The baud rate is derived from the MCU system clock by a
modulus counter. Writing a value of zero to SCBR[12:0] disables the baud rate gener-
ator. Baud rate is calculated as follows:
SCI Baud Rate = _{3----2-----×}----S----C-f--^s--B-^y--^s-R----[--1---2---:--0----]
or
SCBR[12:0] = _{3----2-----×}----S----C-----I---B----a---u--f-^s-d--^y--^s-R----a---t--e-----D----e----s---i-r--e---d--
where SCBR[12:0] is in the range {1, 2, 3, ..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchro-
nize with an incoming data stream. The SCI baud rate generator produces a receive
time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI de-
termines the position of bit boundaries from transitions within the received waveform,
and adjusts sampling points to the proper positions within the bit period.
9.4.3.4 Parity Checking
The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects
received and transmitted data. The PE bit in SCCR1 determines whether parity check-
ing is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a
frame is used for the parity function. For transmitted data, a parity bit is generated; for
received data, the parity bit is checked. When parity checking is enabled, the PF bit in
the SCI status register (SCSR) is set if a parity error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size. Table 9-5 shows possible data and parity formats.
9-26
QUEUED SERIAL MODULE
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M68HC16 Z SERIES
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