MC68HC16Z1 Datasheet, PDF (400/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
BOOT — Boot ROM Control
Reset state of BOOT is specified at mask time. This is a read-only bit.
0 = ROM responds to bootstrap word locations during reset vector fetch.
1 = ROM does not respond to bootstrap word locations during reset vector fetch.
Bootstrap operation is overridden if STOP = 1 at reset.
LOCK — Lock Registers
The reset state of LOCK is specified at mask time. If the reset state of the LOCK is
zero, it can be set once after reset to allow protection of the registers after initialization.
Once the LOCK bit is set, it cannot be cleared again until after a reset. LOCK protects
the ASPC and WAIT fields, as well as the ROMBAL and ROMBAH registers. ASPC,
ROMBAL and ROMBAH are also protected by the STOP bit.
0 = Write lock disabled. Protected registers and fields can be written.
1 = Write lock enabled. Protected registers and fields cannot be written.
EMUL — Emulation Mode Control
0 = Normal ROM operation
1 = Accesses to the ROM array are forced external, allowing memory selected by
the CSM pin to respond to the access.
Because the MC68HC16Z2 and the MC68HC16Z3 do not support ROM emulation
mode, this bit should never be set.
ASPC[1:0] — ROM Array Space
The ASPC field limits access to the SRAM array in microcontrollers that support sep-
arate user and supervisor operating modes. ASPC1 has no effect because the CPU16
operates in supervisor mode only. This bit may be read or written at any time. The
reset state of ASPC[1:0] is specified at mask time. Table D-22 shows ASPC[1:0] en-
coding.
Table D-22 ROM Array Space Field
ASPC[1:0]
X0
X1
State Specified
Program and data accesses
Program access only
WAIT[1:0] — Wait States Field
WAIT[1:0] specifies the number of wait states inserted by the MRM during ROM array
accesses. The reset state of WAIT[1:0] is user specified. The field can be written only
if LOCK = 0 and STOP = 1. Table D-23 shows the wait states field.
Table D-23 Wait States Field
WAIT[1:0]
00
01
10
11
Number of
Wait States
0
1
2
–1
Clocks per Transfer
3
4
5
2
D-26
REGISTER SUMMARY
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M68HC16 Z SERIES
USER’S MANUAL