MC68HC16Z1 Datasheet, PDF (173/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
SPACE[1:0] determines the address space in which a chip-select is asserted. An ac-
cess must have the space type represented by the SPACE[1:0] encoding in order for
a chip-select signal to be asserted.
IPL[2:0] contains an interrupt priority mask that is used when chip-select logic is set to
trigger on external interrupt acknowledge cycles. When SPACE[1:0] is set to %00
(CPU space), interrupt priority (ADDR[3:1]) is compared to the IPL field. If the values
are the same, and other option register constraints are satisfied, a chip-select signal
is asserted. This field only affects the response of chip-selects and does not affect in-
terrupt recognition by the CPU. Encoding %000 in the IPL field causes a chip-select
signal to be asserted regardless of interrupt acknowledge cycle priority, provided all
other constraints are met.
The AVEC bit is used to make a chip-select respond to an interrupt acknowledge cy-
cle. If the AVEC bit is set, an autovector will be selected for the particular external
interrupt being serviced. If AVEC is zero, the interrupt acknowledge cycle will be ter-
minated with DSACK, and an external vector number must be supplied by an external
device.
5.9.1.4 PORTC Data Register
The PORTC data register latches data for PORTC pins programmed as discrete out-
puts. When a pin is assigned as a discrete output, the value in this register appears at
the output. PC[6:0] correspond to CS[9:3]. Bit 7 is not used. Writing to this bit has no
effect, and it always reads zero.
5.9.2 Chip-Select Operation
When the MCU makes an access, enabled chip-select circuits compare the following
items:
• Function codes to SPACE fields, and to the IP mask if the SPACE field encoding
is not for CPU space.
• Appropriate address bus bits to base address fields.
• Read/write status to R/W fields.
• ADDR0 and/or SIZ[1:0] bits to BYTE field (16-bit ports only).
• Priority of the interrupt being acknowledged (ADDR[3:1]) to IPL fields (when the
access is an interrupt acknowledge cycle).
When a match occurs, the chip-select signal is asserted. Assertion occurs at the same
time as AS or DS assertion in asynchronous mode. Assertion is synchronized with
ECLK in synchronous mode. In asynchronous mode, the value of the DSACK field de-
termines whether DSACK is generated internally. DSACK[3:0] also determines the
number of wait states inserted before internal DSACK assertion.
The speed of an external device determines whether internal wait states are needed.
Normally, wait states are inserted into the bus cycle during S3 until a peripheral as-
serts DSACK. If a peripheral does not generate DSACK, internal DSACK generation
must be selected and a predetermined number of wait states can be programmed into
the chip-select option register. Refer to the SIM Reference Manual (SIMRM/AD) for
further information.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
For More Information On This Product,
Go to: www.freescale.com
5-67