MC68HC16Z1 Datasheet, PDF (158/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
DATA8 determines the function of the DSACK[1:0], AVEC, DS, AS, and SIZE pins. If
DATA8 is held low during reset, these pins are assigned to I/O port E.
DATA9 determines the function of interrupt request pins IRQ[7:1] and the clock mode
select pin (MODCLK). When DATA9 is held low during reset, these pins are assigned
to I/O port F.
5.7.3.2 Clock Mode Selection
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency using the clock synthesizer. When MODCLK is held low
during reset, the clock synthesizer is disabled, and an external system clock signal
must be applied. Refer to 5.3 System Clock for more information.
NOTE
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
5.7.3.3 Breakpoint Mode Selection
Background debug mode (BDM) is enabled when the breakpoint (BKPT) pin is sam-
pled at a logic level zero at the release of RESET. Subsequent assertion of the BKPT
pin or the internal breakpoint signal (for instance, the execution of the CPU16 BKPT
instruction) will place the CPU16 in BDM.
If BKPT is sampled at a logic level one at the rising edge of RESET, BDM is disabled.
Assertion of the BKPT pin or execution of the BKPT instruction will result in normal
breakpoint exception processing.
BDM remains enabled until the next system reset. BKPT is relatched on each rising
transition of RESET. BKPT is internally synchronized and must be held low for at least
two clock cycles prior to RESET negation for BDM to be enabled. BKPT assertion logic
must be designed with special care. If BKPT assertion extends into the first bus cycle
following the release of RESET, the bus cycle could inadvertently be tagged with a
breakpoint.
Refer to 4.14.4 Background Debug Mode and the CPU16 Reference Manual
(CPU16RM/AD) for more information on background debug mode. Refer to the SIM
Reference Manual (SIMRM/AD) and APPENDIX A ELECTRICAL CHARACTERIS-
TICS for more information concerning BKPT signal timing.
5.7.4 MCU Module Pin Function During Reset
Usually, module pins default to port functions and input/output ports are set to input
state. This is accomplished by disabling pin functions in the appropriate control regis-
ters and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 5-20 is a summary of mod-
ule pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register
function and reset state.
5-52
SYSTEM INTEGRATION MODULE
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M68HC16 Z SERIES
USER’S MANUAL