MC68HC16Z1 Datasheet, PDF (250/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
10.3.4.2 CPHA = 1 Transfer Format
Figure 10-4 is a timing diagram of an 8-bit, MSB-first SPI transfer in which CPHA
equals one. Two waveforms are shown for SCK, one for CPOL equal to zero and an-
other for CPOL equal to one. The diagram may be interpreted as a master or slave
timing diagram since the SCK, MISO and MOSI pins are directly connected between
the master and the slave. The MISO signal shown is the output from the slave and the
MOSI signal shown is the output from the master. The SS line is the slave select input
to the slave.
SCK CYCLE #
(FOR REFERENCE)
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
SS (TO SLAVE)
MSB
6
5
4
3
2
1
LSB
*
MSB
6
5
4
3
2
1
LSB
* NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER
Figure 10-4 CPHA = 1 SPI Transfer Format
CPHA = 1 SPI TRANSFER
For a master, writing to the SPDR initiates the transfer. For a slave, the first edge of
SCK indicates the start of a transfer. The SPI is left-shifted on the first and each suc-
ceeding odd clock edge, and data is latched on the second and succeeding even clock
edges.
SCK is inactive for the last half of the eighth SCK cycle. For a master, SPIF is set at
the end of the eighth SCK cycle (after the seventeenth SCK edge). Since the last SCK
edge occurs in the middle of the eighth SCK cycle, however, the slave has no way of
knowing when the end of the last SCK cycle occurs. The slave therefore considers the
transfer complete after the last bit of serial data has been sampled, which corresponds
to the middle of the eighth SCK cycle.
When CPHA is one, the SS line may remain at its active low level between transfers.
This format is sometimes preferred in systems having a single fixed master and only
one slave that needs to drive the MISO data line.
10-10
MULTICHANNEL COMMUNICATION INTERFACE
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M68HC16 Z SERIES
USER’S MANUAL