MC68HC16Z1 Datasheet, PDF (391/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table D-10 CSPAR1 Pin Assignments
CSPAR1 Field
CS10PA[1:0]
CS9PA[1:0]
CS8PA[1:0]
CS7PA[1:0]
CS6PA[1:0]
Chip-Select Signal
CS10
CS9
CS8
CS7
CS6
Alternate Signal
ADDR23¹
ADDR22¹
ADDR21¹
ADDR20¹
ADDR19
Discrete Output
ECLK
PC6
PC5
PC4
PC3
NOTES:
1. On the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless externally
driven.
The reset state of DATA[7:3] determines whether pins controlled by CSPAR1 are ini-
tially configured as high-order address lines or chip-selects. Table D-11 shows the
correspondence between DATA[7:3] and the reset configuration of CS[10:6]/
ADDR[23:19]. This register may be read or written at any time. After reset, software
may enable one or more pins as discrete outputs.
Table D-11 Reset Pin Function of CS[10:6]
DATA7
1
1
1
1
1
0
Data Bus Pins at Reset
DATA6 DATA5 DATA4
1
1
1
1
1
1
1
1
0
1
0
X
0
X
X
X
X
X
Chip-Select/Address Bus Pin Function
DATA3
CS10/ CS9/ CS8/ CS7/ CS6/
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
1
CS10 CS9
CS8
CS7
CS6
0
CS10 CS9
CS8
CS7 ADDR19
X
CS10 CS9
CS8 ADDR20 ADDR19
X
CS10 CS9 ADDR21 ADDR20 ADDR19
X
CS10 ADDR22 ADDR21 ADDR20 ADDR19
X ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
D.2.18 Chip-Select Base Address Register Boot
CSBARBT — Chip-Select Base Address Register Boot
15
14
ADDR ADDR
23
22
RESET:
0
0
13
ADDR
21
0
12
ADDR
20
0
11
ADDR
19
0
10
ADDR
18
0
9
ADDR
17
0
8
ADDR
16
0
7
ADDR
15
0
6
ADDR
14
0
5
ADDR
13
0
4
ADDR
12
0
3
ADDR
11
0
$YFFA48
2
1
0
BLKSZ[2:0]
1
1
1
D.2.19 Chip-Select Base Address Registers
CSBAR[0:10] — Chip-Select Base Address Registers
$YFFA4C–$YFFA74
15
14
ADDR ADDR
23
22
RESET:
0
0
13
ADDR
21
0
12
ADDR
20
0
11
ADDR
19
0
10
ADDR
18
0
9
ADDR
17
0
8
ADDR
16
0
7
ADDR
15
0
6
ADDR
14
0
5
ADDR
13
0
4
ADDR
12
0
3
ADDR
11
0
2
1
0
BLKSZ[2:0]
0
0
0
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
For More Information On This Product,
Go to: www.freescale.com
D-17