MC68HC16Z1 Datasheet, PDF (147/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
CPU SPACE CYCLES
FUNCTION
CODE
ADDRESS BUS
BREAKPOINT
ACKNOWLEDGE
20
111
23
19 16
4 210
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPT# T 0
LOW POWER
STOP BROADCAST
20
111
23
19 16
0
000000111111111111111110
INTERRUPT
ACKNOWLEDGE
20
111
23
19 16
0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LEVEL 1
CPU SPACE
TYPE FIELD
Figure 5-14 CPU Space Address Encoding
CPU SPACE CYC TIM
5.6.4.1 Breakpoint Acknowledge Cycle
Breakpoints stop program execution at a predefined point during system development.
In M68HC16 Z-series MCUs, breakpoints are treated as a type of exception process-
ing. Breakpoints can be used alone or in conjunction with background debug mode.
M68HC16 Z series MCUs have only one source and type of breakpoint. This is a hard-
ware breakpoint initiated by assertion of the BKPT input. Other modular microcontrol-
lers may have more than one source or type. The breakpoint acknowledge cycle
discussed here is the bus cycle that occurs as a part of breakpoint exception process-
ing when a breakpoint is initiated while background debug mode is not enabled.
BKPT is sampled on the same clock phase as data. BKPT is valid, the data is tagged
as it enters the CPU16 pipeline. When BKPT is asserted while data is valid during an
instruction prefetch, the acknowledge cycle occurs immediately after that instruction
has executed. When BKPT is asserted while data is valid during an operand fetch, the
acknowledge cycle occurs immediately after execution of the instruction during which
it is latched. If BKPT is asserted for only one bus cycle and a pipe flush occurs before
BKPT is detected by the CPU16, no acknowledge cycle occurs. To ensure detection,
BKPT should be asserted until a breakpoint acknowledge cycle is recognized.
When BKPT assertion is acknowledged by the CPU16, the MCU performs a word read
from CPU space address $00001E. This corresponds to the breakpoint number field
(ADDR[4:2]) and the type bit (T) being set to all ones (source 7, type 1). If this bus cycle
is terminated by BERR or by DSACK, the MCU performs breakpoint exception pro-
cessing. Refer to Figure 5-15 for a flowchart of the breakpoint operation. Refer to the
SIM Reference Manual (SIMRM/AD) for further information.
M68HC16 Z SERIES
USER’S MANUAL
SYSTEM INTEGRATION MODULE
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