MC68HC16Z1 Datasheet, PDF (420/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table D-34 Effect of DDRQS on QSM Pin Function
QSM Pin
MISO
MOSI
SCK¹
PCS0/SS
PCS[1:3]
TXD²
RXD
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
—
—
DDRQS Bit
DDQS0
DDQS1
DDQS2
DDQS3
DDQS[4:6]
DDQS7
None
Bit State
0
1
0
1
0
1
0
1
—
—
0
1
0
1
0
1
0
1
X
NA
Pin Function
Serial data input to QSPI
Disables data input
Disables data output
Serial data output from QSPI
Disables data output
Serial data output from QSPI
Serial data input to QSPI
Disables data input
Clock output from QSPI
Clock input to QSPI
Assertion causes mode fault
Chip-select output
QSPI slave select input
Disables slave select Input
Disables chip-select output
Chip-select outputs enabled
No effect
No effect
Serial data output from SCI
Serial data input to SCI
NOTES:
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it
becomes the QSPI serial clock SCK.
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set in SCCR1), in
which case it becomes the SCI serial data output TXD.
DDQS7 determines the direction of PQS7 only when the SCI transmitter is disabled.
When the SCI transmitter is enabled, PQS7 is the TXD output.
D.6.10 QSPI Control Register 0
SPCR0 — QSPI Control Register 0
$YFFC18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSTR WOMQ
BITS[3:0]
CPOL CPHA
SPBR[7:0]
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
SPCR0 contains parameters for configuring the QSPI and enabling various modes of
operation. SPCR0 must be initialized before QSPI operation begins. Writing a new val-
ue to SPCR0 while the QSPI is enabled disrupts operation.
MSTR — Master/Slave Mode Select
0 = QSPI is a slave device.
1 = QSPI is the system master.
D-46
REGISTER SUMMARY
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M68HC16 Z SERIES
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