MC68HC16Z1 Datasheet, PDF (410/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
D.5.6 ADC Status Register
ADCSTAT — ADC Status Register
$YFF70E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCF
NOT USED
CCTR[2:0]
CCF[7:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
ADCSTAT contains information related to the status of a conversion sequence.
SCF — Sequence Complete Flag
0 = Sequence not complete
1 = Sequence complete
SCF is set at the end of the conversion sequence when SCAN is cleared, and at the
end of the first conversion sequence when SCAN is set. SCF is cleared when ADCTL1
is written and a new conversion sequence begins.
CCTR[2:0] — Conversion Counter
This field reflects the contents of the conversion counter pointer in either four or eight
count conversion sequence. The value corresponds to the number of the next result
register to be written, and thus indicates which channel is being converted.
CCF[7:0] — Conversion Complete Flags
Each bit in this field corresponds to an A/D result register (for example, CCF7 to
RSLT7). A bit is set when conversion for the corresponding channel is complete, and
remains set until the associated result register is read.
D.5.7 Right Justified, Unsigned Result Register
RJURR — Right-Justified, Unsigned Result Register
$YFF710–$YFF71F
15
10
9
8
7
6
5
4
3
2
1
0
NOT USED
10
10 8/10 8/10 8/10 8/10 8/10 8/10 8/10 8/10
Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolu-
tion. For 8-bit conversions, bits [7:0] contain data and bits [9:8] are zero. Bits [15:10]
always return zero when read.
D.5.8 Left Justified, Signed Result Register
LJSRR — Left Justified, Signed Result Register
15
14
13
12
11
10
9
8
7
6
5
8/10 8/10 8/10 8/10 8/10 8/10 8/10 8/10 10
10
$YFF720–$YFF72F
0
NOT USED
Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution.
For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Although the ADC
is unipolar, it is assumed that the zero point is halfway between low and high reference
when this format is used (V_RH – V_RL/2). For positive input, bit 15 = 0. For negative in-
put, bit 15 = 1. Bits [5:0] always return zero when read.
D-36
REGISTER SUMMARY
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M68HC16 Z SERIES
USER’S MANUAL