MC68HC16Z1 Datasheet, PDF (405/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
PADA[7:0] — Port ADA Data Pins
A read of PADA[7:0] returns the logic level of the port ADA pins. If an input is not at an
appropriate logic level (that is, outside the defined levels), the read is indeterminate.
Use of a port ADA pin for digital input does not preclude its simultaneous use as an
analog input.
D.5.4 ADC Control Register 0
ADCTL0 — ADC Control Register 0
$YFF70A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
RES10
STS[1:0]
PRS[4:0]
RESET:
0
0
0
0
0
0
1
1
ADCTL0 is used to select 8- or 10-bit conversions, sample time, and ADC clock fre-
quency. Writes to it have immediate effect.
RES10 — 10-Bit Resolution
0 = 8-bit conversion
1 = 10-bit conversion
Conversion results are appropriately aligned in result registers to reflect the number of
bits.
STS[1:0] — Sample Time Selection
Total conversion time is the sum of initial sample time, transfer time, final sample time,
and resolution time. Initial sample time is fixed at two ADC clocks. Transfer time is
fixed at two ADC clocks. Resolution time is fixed at ten ADC clocks for an 8-bit con-
version and twelve ADC clocks for a 10-bit conversion. Final sample time is deter-
mined by the STS[1:0] field. Refer to Table D-26.
Table D-26 Sample Time Selection
STS[1:0]
00
01
10
11
Sample Time
2 ADC Clock Periods
4 ADC Clock Periods
8 ADC Clock Periods
16 ADC Clock Periods
PRS[4:0] — Prescaler Rate Selection
The ADC clock is derived from the system clock by a programmable prescaler. ADC
clock period is determined by the value of the PRS field in ADCTL0. The prescaler has
two stages. The first stage is a 5-bit modulus counter. It divides the system clock by
any value from two to 32 (PRS[4:0] = %00000 to %11111). The second stage is a di-
vide-by-two circuit. Refer to Table D-27.
M68HC16 Z SERIES
USER’S MANUAL
REGISTER SUMMARY
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D-31