MC68HC16Z1 Datasheet, PDF (243/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
To ensure that the MCCI stops in a known state, assert the STOP bit before executing
the CPU LPSTOP instruction. Before asserting the STOP bit, disable the SPI (clear
the SPE bit) and disable the SCI receivers and transmitters (clear the RE and TE bits).
Complete transfers in progress before disabling the SPI and SCI interfaces.
Once the STOP bit is asserted, it can be cleared by system software or by reset.
10.2.1.2 Privilege Levels
The supervisor bit (SUPV) in the MMCR has no effect since the CPU16 operates only
in the supervisor mode.
10.2.1.3 MCCI Interrupts
The interrupt request level of each of the three MCCI interfaces can be programmed
to a value of zero (interrupts disabled) through seven (highest priority). These levels
are selected by the ILSCIA and ILSCIB fields in the SCI interrupt level register (ILSCI)
and the ILSPI field in the SPI interrupt level register (ILSPI). In case two or more MCCI
submodules request an interrupt simultaneously and are assigned the same interrupt
request level, the SPI submodule is given the highest priority and SCIB is given the
lowest.
When an interrupt is requested which is at a higher level than the interrupt mask in the
CPU status register, the CPU initiates an interrupt acknowledge cycle. During this cy-
cle, the MCCI compares its interrupt request level to the level recognized by the CPU.
If a match occurs, arbitration with other modules begins.
Interrupting modules present their arbitration number on the IMB, and the module with
the highest number wins. The arbitration number for the MCCI is programmed into the
interrupt arbitration (IARB) field of the MMCR. Each module should be assigned a
unique arbitration number. The reset value of the IARB field is $0, which prevents the
MCCI from arbitrating during an interrupt acknowledge cycle. The IARB field should
be initialized by system software to a value from $F (highest priority) through $1 (low-
est priority). Otherwise, the CPU identifies any interrupts generated as spurious and
takes a spurious-interrupt exception.
If the MCCI wins the arbitration, it generates an interrupt vector that uniquely identifies
the interrupting serial interface. The six MSBs are read from the interrupt vector (INTV)
field in the MCCI interrupt vector register (MIVR). The two LSBs are assigned by the
MCCI according to the interrupting serial interface, as indicated in Table 10-1.
Table 10-1 MCCI Interrupt Vectors
Interface
SCIA
SCIB
SPI
INTV[1:0]
00
01
10
M68HC16 Z SERIES
USER’S MANUAL
MULTICHANNEL COMMUNICATION INTERFACE
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