MC68HC16Z1 Datasheet, PDF (150/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table 5-17 DSACK, BERR, and HALT Assertion Results
Type of
Termination
Control
Signal
NORMAL
HALT
BUS ERROR
1
BUS ERROR
2
BUS ERROR
3
BUS ERROR
4
DSACK
BERR
HALT
DSACK
BERR
HALT
DSACK
BERR
HALT
DSACK
BERR
HALT
DSACK
BERR
HALT
DSACK
BERR
HALT
Asserted on Rising
Edge of State
S¹
S+2
A²
RA⁴
NA³
NA
NA
X⁵
A
RA
NA
NA
A/RA
RA
NA/A
X
A
RA
NA
X
A
X
A
RA
NA
NA
NA/A
X
A
RA
A/S
RA
A
X
NA
A
NA
A
Description
of Result
Normal cycle terminate and continue.
Normal cycle terminate and halt.
Continue when HALT is negated.
Terminate and take bus error exception.
Terminate and take bus error exception.
Terminate and take bus error exception.
Terminate and take bus error exception.
NOTES:
1. S = The number of current even bus state (for example, S2, S4, etc.)
2. A = Signal is asserted in this bus state.
3. NA = Signal is not asserted in this state.
4. RA = Signal was asserted in previous state and remains asserted in this state.
5. X = Don’t care
5.6.5.1 Bus Errors
The CPU16 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU16 detects assertion of the IMB BERR signal.
BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several
factors:
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
BERR is asserted.
• Whether BERR is asserted during a program space access or a data space
access.
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.
5-44
SYSTEM INTEGRATION MODULE
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