MSC8144EC Datasheet, PDF (74/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Hardware Design Considerations
PCI_TRDY
V_DDIO
Table 69. Connectivity of PCI Related Pins When PCI Is Not Used
Signal Name
Pin Connection
V_DDIO
3.3 V
3.4.8 Miscellaneous Pins
Table 71 lists the board connections for the pins if they are required by the system design. Table 71 assumes that the alternate
function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected
function.
Table 70. Connectivity of Individual Pins When They Are Not Required
Signal Name
Pin Connection
CLKOUT
NC
EE0
GND
EE1
NC
GPIO[0–31]
NC
SCL
See the GPIO connectivity guidelines in this table.
SDA
See the GPIO connectivity guidelines in this table.
INT_OUT
NC
IRQ[0–15]
See the GPIO connectivity guidelines in this table.
NMI
NMI_OUT
V_DDIO
NC
RC[0–16]
GND
RC_LDF
NC
STOP_BS
GND
TCK
GND
TDI
GND
TDO
NC
TMR[0–4]
See the GPIO connectivity guidelines in this table.
TMS
GND
TRST
GND
URXD
See the GPIO connectivity guidelines in this table.
UTXD
See the GPIO connectivity guidelines in this table.
V_DDIO
Note:
3.3 V
When using I/O multiplexing mode 5 or 6, tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND.
Note: For details on configuration, see the MSC8144EC Reference Manual. For additional information, refer to the
MSC8144 Design Checklist (AN3202).
3.5 External DDR SDRAM Selection
TBD
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
74
Freescale Semiconductor