MSC8144EC Datasheet, PDF (57/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

ETHCLOCK
ETHSYNC_IN
ETHRXD
t_SMDVKH
Valid
t_SMDXKH
ETHSYNC
ETHTXD
Valid
t_SMXR
Valid
Figure 31. SMII Mode Signal Timing
2.7.10.6 RGMII AC Timing Specifications
Table 50 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 50. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver) ²
Clock cycle duration ³
Duty cycle for 1000Base-T ^{4, 5}
Duty cycle for 10BASE-T and 100BASE-TX ^{3, 5}
t_SKEWT
-0.5
—
0.5
ns
t_SKEWR
0.9
—
2.6
ns
t_RGT
7.2
8.0
8.8
ns
t_RGTH/t_RGT
45
50
55
%
t_RGTH/t_RGT
40
50
60
%
Rise time (20%–80%)
t_RGTR
—
—
0.75
ns
Fall time (20%–80%)
GTX_CLK125 reference clock period
t_RGTF
t_G12 ⁶
—
—
0.75
ns
—
8.0
—
ns
GTX_CLK125 reference clock duty cycle
t_G125H/t_G125
47
—
53
%
Notes: 1. At recommended operating conditions with LV_DD of 2.5 V +/- 5%.
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will
be added to the associated clock signal.
3. For 10 and 100 Mbps, t_RGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGT of the lowest speed transitioned
between.
5. Duty cycle reference is L_Vdd/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. GCR4 should be programmed as 0x00001004.
Table 51 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 51. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver) ²
Clock cycle duration ³
Duty cycle for 1000Base-T ^{4, 5}
Duty cycle for 10BASE-T and 100BASE-TX ^{3, 5}
Rise time (20%–80%)
Fall time (20%–80%)
GTX_CLK125 reference clock period
Symbol
Min
Typ
Max
Unit
t_SKEWT
–2.6
—
–0.9
ns
t_SKEWR
–0.5
—
0.5
ns
t_RGT
7.2
8.0
8.8
ns
t_RGTH/t_RGT
45
50
55
%
t_RGTH/t_RGT
40
50
60
%
t_RGTR
—
—
0.75
ns
t_RGTF
t_G12 ⁶
—
—
0.75
ns
—
8.0
—
ns
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
57