MSC8144EC Datasheet, PDF (53/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

2.7.9 Timer Timing
Table 44. Timer Timing
Characteristics
TIMERx frequency
TIMERx Input high phase
TIMERx Output low phase
Figure 24 shows the timer input AC timing
T_TMREFCLK
T_TMCH
T_TMCL
Symbol
T_TMREFCLK
T_TMCH
T_TMCL
Min
10.0
4.0
4.0
Unit
ns
ns
ns
TIMERx (Input)
Figure 24. Timer Timing
2.7.10 Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144EC
Reference Manual.
2.7.10.1 Management Interface Timing
Table 45. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
ETHMDC clock pulse width high
ETHMDC to ETHMDIO delay²
t_MDCH
32
—
ns
t_MDKHDX
10
70
ns
ETHMDIO to ETHMDC rising edge set-up time
t_MDDVKH
7
—
ns
ETHMDC rising edge to ETHMDIO hold time
t_MDDXKH
0
—
ns
ETHMDC rise time.
t_MDCR
—
10
ns
ETHMDC fall time.
t_MDHF
—
10
ns
Notes: 1. Program the ETHMDC frequency (f_MDC) to a maximum value of 2.5 MHz (400 ns period for t_MDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz, to
achieve f_MDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144EC Reference Manual
for configuration details.
2. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
53