MSC8144EC Datasheet, PDF (46/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
Table 37. Receiver AC Timing Specifications—1.25 GBaud (continued)
Characteristic
Total Jitter Tolerance
Multiple Input Skew
Bit Error Rate
Unit Interval
Symbol
J_T
S_MI
BER
UI
Range
Min
Max
0.65
24
10^–12
800
800
Unit
Notes
UI_PP
ns
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Skew at the receiver input between lanes of a
multilane link
ps ±100 ppm
Table 38. Receiver AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Differential Input Voltage
V_IN
Deterministic Jitter Tolerance
J_D
Combined Deterministic and Random
J_DR
Jitter Tolerance
Total Jitter Tolerance
J_T
Multiple Input Skew
Bit Error Rate
Unit Interval
S_MI
BER
UI
Range
Min
Max
200
1600
0.37
0.55
Unit
Notes
mV_PP
UI_PP
UI_PP
Measured at receiver
Measured at receiver
Measured at receiver
0.65
UI_PP Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
24
10^–12
ns Skew at the receiver input between lanes of a
multilane link
400
400
ps ±100 ppm
Table 39. Receiver AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Differential Input Voltage
V_IN
Deterministic Jitter Tolerance
J_D
Combined Deterministic and Random
J_DR
Jitter Tolerance
Total Jitter Tolerance
J_T
Multiple Input Skew
S_MI
Range
Min
Max
200
1600
0.37
0.55
Unit
Notes
mV_PP
UI_PP
UI_PP
Measured at receiver
Measured at receiver
Measured at receiver
0.65
UI_PP Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 14. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
22
ns Skew at the receiver input between lanes of a
multilane link
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
46
Freescale Semiconductor