MSC8144EC Datasheet, PDF (29/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
all four cores. It was created using CodeWarrior^® 3.0. These values are provided as examples only. Power consumption is
application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining
proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Section 3 of
this document.
At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V AV_DD supplies for the MSC8144EC
PLLs.
Table 7. MSC8144EC PLLs Power Dissipation
PLL supply
Typical
Maximum
Unit
V_DDPLL0
TBD
10
mW
V_DDPLL1
TBD
10
mW
V_DDPLL2
TBD
10
mW
Note: Typical value is based on V_DDPLLX = 1.0 V, T_A = 70°C, T_J = 105°C.
2.6 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8144EC.
2.6.1 DDR SDRAM DC Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144EC.
Note: DDR SDRAM uses V_DDDDR(typ) = 2.5 V and DDR2 SDRAM uses V_DDDDR(typ) = 1.8 V.
2.6.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144EC when
V_DDDDR(typ) = 1.8 V.
Table 8. DDR2 SDRAM DC Electrical Characteristics for V_DDDDR (typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
I/O supply voltage¹
I/O reference voltage²
I/O termination voltage³
V_DDDDR
1.7
1.9
V
MV_REF
0.49 × V_DDDDR
0.51 × V_DDDDR
V
V_TT
MV_REF – 0.04
MV_REF + 0.04
V
Input high voltage
V_IH
MV_REF + 0.125
V_DDDDR + 0.3
V
Input low voltage
Output leakage current⁴
V_IL
–0.3
MV_REF – 0.125
V
I_OZ
–50
50
μA
Output high current (V_OUT = 1.420 V)
I_OH
–13.4
—
mA
Output low current (V_OUT = 0.280 V)
I_OL
13.4
—
mA
Notes: 1. V_DDDDR is expected to be within 50 mV of the DRAM V_DD at all times.
2. MV_REF is expected to be equal to 0.5 × V_DDDDR, and to track V_DDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MV_REF may not exceed ±2% of the DC value.
3. V_TT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MV_REF. This rail should track variations in the DC level of V_DDDDR.
4. Output leakage is measured with all outputs are disabled, 0 V ≤ V_OUT ≤ V_DDDDR.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
29