MSC8144EC Datasheet, PDF (6/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

1.2 Signal List By Ball Location
Table 1 presents the signal list sorted by ball number. The functionality of multi-functional (multiplexed) pins is separated for
each mode. When designing a board, make sure that the reference supply for each signal is appropriately considered. The
specified reference supply must be tied to the voltage level specified in this document if any of the related signal functions are
used (active).
Ball
Number
Signal Name
A2 GND
A3 GE2_RX_ER/PCI_AD31
A4 V_DDGE2
A5 GE2_RX_DV/PCI_AD30
A6 GE2_TD0/PCI_CBE0
A7 SRIO_IMP_CAL_RX
A8 Reserved¹
A9 Reserved¹
A10 Reserved¹
A11 Reserved¹
A12 SRIO_RXD0
A13 V_DDSXC
A14 SRIO_RXD1
A15 V_DDSXC
A16 SRIO_REF_CLK
A17 V_DDRIOPLL
A18 GND_SXC
A19 SRIO_RXD2/
GE1_SGMII_RX
A20 V_DDSXC
A21 SRIO_RXD3/
GE2_SGMII_RX
A22 V_DDSXC
A23 SRIO_IMP_CAL_TX
A24 MDQ28
A25 MDQ29
A26 MDQ30
A27 MDQ31
A28 MDQS3
B1 Reserved¹
B2 GE2_TD1/PCI_CBE1
B3 GE2_TX_EN/PCI_CBE2
B4 GE_MDIO
B5 GND
B6 GE_MDC
B7 GND_SXC
B8 Reserved¹
B9 Reserved¹
Table 1. Signal List by Ball Number
Power-
On
Reset
Value
0 (000)
1 (001)
I/O Multiplexing Mode²
2 (010) 3 (011) 4 (100) 5 (101)
6 (110)
7 (111)
Ref.
Supply
Ethernet 2
Ethernet 2
Ethernet 2
PCI
Ethernet 2
PCI
Ethernet 2
PCI
Ethernet 2
SGMII support on SERDES is enabled by Reset Configuration Word
GND
V_DDGE2
V_DDGE2
V_DDGE2
V_DDGE2
V_DDSXC
—
—
—
—
V_DDSXC
V_DDSXC
V_DDSXC
V_DDSXC
V_DDSXC
GND_RIOPLL
GND_SXC
V_DDSXC
SGMII support on SERDES is enabled by Reset Configuration Word
V_DDSXC
V_DDSXC
Ethernet 2
Ethernet 2
PCI
PCI
Ethernet
Ethernet
Ethernet 2
Ethernet 2
V_DDSXC
V_DDSXP
V_DDDDR
V_DDDDR
V_DDDDR
V_DDDDR
V_DDDDR
—
V_DDGE2
V_DDGE2
V_DDGE2
GND
V_DDGE2
GND_SXC
—
—
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
6
Freescale Semiconductor