MSC8144EC Datasheet, PDF (67/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Hardware Design Considerations
Table 56. Connectivity of DDR Related Pins When the DDR Interface Is Not Used (continued)
Signal Name
Pin Connection
ECC_MDQS
NC
ECC_MDQS
NC
MV_REF
GND
V_DDDDR
GND
Note:
If the DDR controller is not used, disable the internal DDR clock by writing a 1 to the CLK11DIS bit in the System Clock Control
Register (SCCR[CLK!11DIS]). See Chapter 7, Clocks, in the MSC8144EC Reference Manual for details.
3.4.1.2 16-Bit DDR Memory Only
Table 58 lists unused pin connection when using 16-bit DDR memory. The 16 most significant data lines are not used.
Table 57. Connectivity of DDR Related Pins When Using 16-bit DDR Memory Only
MDQ[0–15]
MDQ[16–31]
MDQS[0–1]
MDQS[2–3]
MDQS[0–1]
MDQS[2–3]
MA[0–15]
MCK[0–2]
MCK[0–2]
MCS[0–1]
MDM[0–1]
MDM[2–3]
MBA[0–2]
MCAS
MCKE[0–1]
MODT[0–1]
MDIC[0–1]
MRAS
MWE
MV_REF
V_DDDDR
Signal Name
Pin connection
in use
pull-up to V_DDDDR
in use
pull-down to GND
in use
pull-up to V_DDDDR
in use
in use
in use
in use
in use
NC
in use
in use
in use
in use
in use
in use
in use
1/2*V_DDDDR
2.5 V or 1.8 V
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
67