MSC8144EC Datasheet, PDF (56/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Figure 29 shows the RMII transmit and receive AC timing diagram.
t_RMX
t_RMXR
REF_CLK
TXD[1–0]
TX_EN
t_RMXH
t_RMXF
RXD[1–0]
CRS_DV
RX_ER
t_RMRDVKH
t_RMTKHDX
Valid Data
t_RMRDXKH
Figure 29. RMII Transmit and Receive AC Timing
Figure 30 provides the AC test load.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_DDGE/2
Figure 30. AC Test Load
2.7.10.5 SMII AC Timing Specification
Table 49. SMII Mode Signal Timing
Characteristics
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time
ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay
Notes: 1. Typical REF_CLK clock period is 8ns
2. Measured using a 5 pF load.
3. Measured using a 15 pF load
4. REF_CLK duty cycle is TBD.
5. Program GCR4 as 0x00002008
Symbol
t_SMDVKH
t_SMDXKH
t_SMXR
Min
Max
Unit
1.5
—
ns
1.0
—
ns
1.5
5.0
ns
Figure 31 provides the AC test load.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
56
Freescale Semiconductor