MSC8144EC Datasheet, PDF (58/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Table 51. RGMII with No On-Board Delay AC Timing Specifications (continued)
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GTX_CLK125 reference clock duty cycle
t_G125H/t_G125
47
—
53
%
Notes: 1. At recommended operating conditions with LV_DD of 2.5 V +/- 5%.
2. This implies that PC board design will require clocks to be routed with no additional trace delay
3. For 10 and 100 Mbps, t_RGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGT of the lowest speed transitioned
between.
5. Duty cycle reference is L_Vdd/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. GCR4 should be programmed as 0x0004C130.
Figure 32 shows the RGMII AC timing and multiplexing diagrams.
GTX_CLK
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[3:0]
TXD[8:5]
TXD[7:4]
t_RGTH
t_SKEWT
t_RGT
TX_CTL
TX_CLK
(At PHY)
TXD[4]
TXEN
TXD[9]
TXERR
t_SKEWR
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CTL
RX_CLK
(At PHY)
RXD[3:0]
RXD[8:5]
RXD[7:4]
RXD[4]
RXDV
RXD[9]
RXERR
t_SKEWT
Figure 32. RGMII AC Timing and Multiplexing s
t_SKEWR
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
58
Freescale Semiconductor