MSC8144EC Datasheet, PDF (2/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Table of Contents
1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27
2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .27
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29
2.7 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .64
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .65
3.3 Clock and Timing Signal Board Layout Considerations 65
3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66
3.5 External DDR SDRAM Selection . . . . . . . . . . . . . . . . .74
4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
List of Figures
Figure 1. MSC8144EC Block Diagram. . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram 3
Figure 3. MSC8144EC FC-PBGA Package, Top View. . . . . . . . . . 4
Figure 4. MSC8144EC FC-PBGA Package, Bottom View . . . . . . . 5
Figure 5. SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31
Figure 6. Overshoot/Undershoot Voltage for V_IH and V_IL. . . . . . . 34
Figure 7. Start-Up Sequence with V_DD Raised Before V_DDIO with
CLKIN Started with V_DDIO . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Timing for a Reset Configuration Write . . . . . . . . . . . . . 38
Figure 9. Timing for t_DDKHMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10.DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 11.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12.Differential V_PP of Transmitter or Receiver . . . . . . . . . . 42
Figure 13.Transmitter Output Compliance Mask . . . . . . . . . . . . . . 45
Figure 14.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 47
Figure 15.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 48
Figure 16.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17.PCI Input AC Timing Measurement Conditions . . . . . . . 50
Figure 18.PCI Output AC Timing Measurement Condition . . . . . . 50
Figure 19.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 21.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 22.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 23.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 24.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 25.MII Management Interface Timing . . . . . . . . . . . . . . . . . 54
Figure 26.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 27.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 28.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 56
Figure 30.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 31.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 32.RGMII AC Timing and Multiplexing s. . . . . . . . . . . . . . . 58
Figure 33.UTOPIA AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 34.UTOPIA AC Timing (External Clock) . . . . . . . . . . . . . . . 59
Figure 35.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 36.SPI AC Timing in Slave Mode (External Clock). . . . . . . 60
Figure 37.SPI AC Timing in Master Mode (Internal Clock) . . . . . . 61
Figure 38.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 39.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 40.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 41.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 63
Figure 42.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 43.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 44.V_DDM3, V_DDM3IO and V_25M3 Power-on Sequence . . . . . 64
Figure 46.MSC8144EC Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
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Freescale Semiconductor