MSC8144EC Datasheet, PDF (38/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
2.7.3.3 Reset Timing Tables
Table 24 and Figure 8 describe the reset timing for a reset configuration.
Table 24. Timing for a Reset Configuration Write
No.
Characteristics
1 Required external PORESET duration minimum
• 25 MHz <= CLKIN < 44 MHz
• 44 MHz <= CLKIN < 66 MHz
• 66 MHz <= CLKIN < 100 MHz
• 100 MHz <= CLKIN < 133 MHz
2 Delay from de-assertion of external PORESET to HRESET deassertion for
external pins and hard coded RCW
• 25 MHz <= CLKIN < 66 MHz
• 66 MHz <= CLKIN <= 133 MHz
Expression
32/CLKIN
15369/CLKIN
34825/CLKIN
3
Note:
Delay from de-assertion of external PORESET to HRESET deassertion for
loading RCW the I²C interface
• 25 MHz <= CLKIN < 44 MHz
• 44 MHz <= CLKIN < 66 MHz
• 66 MHz <= CLKIN < 100 MHz
• 100 MHz <= CLKIN < 133 MHz
Delay from HRESET deassertion to SRESET deassertion
• REFCLK = 25 MHz to 133 MHz
Timings are not tested, but are guaranteed by design.
92545/CLKIN
107435/CLKIN
124208/CLKIN
157880/CLKIN
16/CLKIN
Max Min Unit
1280
727
ns
728
484
ns
485
320
ns
320
241
ns
615
233
μs
528
262
μs
3702 2103
μs
2441 1627
μs
1882 1242
μs
1579 1187
μs
640
120
ns
PORESET
Input
HRESET
Output (I/O)
SRESET
Output (I/O)
RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG
1
pins must be valid
2
Reset configuration write
sequence during this
period.
3
Figure 8. Timing for a Reset Configuration Write
See also Reset Errata for PLL lock and reset duration.
2.7.4 DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.7.4.1 DDR SDRAM Input Timings
Table 25 provides the input AC timing specifications for the DDR SDRAM when V_DDDDR (typ) = 2.5 V.
Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
AC input low voltage
Parameter
Symbol
Min
Max
Unit
V_IL
—
MV_REF – 0.31
V
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
38
Freescale Semiconductor