MSC8144EC Datasheet, PDF (3/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

DDR Interface 16/32-bit at 400 MHz data rate
512 Kbytes
M2
Memory
Four DSP
Subsystems
128 Kbyte
L2
ICache
JTAG
10 Mbytes
M3
Memory
CLASS
128-bit at
400 MHz
DDR
Controller
QUICC Engine™
Subsystem
Dual RISC
Processors
Ether-
net
Ether-
net ^ATM
SPI
Ser. RapidIO
Subsystem
RMU SRIO
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
Semaphores
Virtual
Interrupts
Boot ROM
I²C
Other
Modules
Eight TDMs
256-Channels each
10/100/1000 Mbps
10/100/1000 Mbps
Note: The arrow direction indicates master or slave.
SPI
16-bit/8-bit
UTOPIA
1x/4x
PCI 32-bit
33/66 MHz
Figure 1. MSC8144EC Block Diagram
Two Internal Buses
(128 bits wide each)
Interrupts
TWB
Bus Interface
IQBus
DQBus
EPIC
Debug Support
OCE30 DPU
Instruction
Cache
SC3400
Core
P-bus
Xa-bus
Xb-bus
Write-
Through
Buffer
(WTB)
Data
Cache
Write-
Back
Buffer
(WBB)
Timer
Task
Protection
Address
Translation
MMU
Figure 2. StarCore SC3400 DSP Core Subsystem Block Diagram
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
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