MSC8144EC Datasheet, PDF (41/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Figure 10 shows the DDR SDRAM output timing diagram.
Electrical Characteristics
MCK[n]
MCK[n]
t_MCK
ADDR/CMD
t_DDKHAS, t_DDKHCS
t_DDKHAX ,t_DDKHCX
Write A0
NOOP
t_DDKHMP
t_DDKHMH
MDQS[n]
MDQ[x]
D0
t_DDKHDX
t_DDKHDS
t_DDKLDS
D1
t_DDKLDX
Figure 10. DDR SDRAM Output Timing
Figure 11 provides the AC test load for the DDR bus.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_DDDDR/2
t_DDKHME
Figure 11. DDR AC Test Load
2.7.5 Serial RapidIO Timing and SGMII Timing
2.7.5.1 AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 29 lists AC requirements.
Table 29. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Parameter Description
REFCLK cycle time
Symbol
t_REF
REFCLK cycle-to-cycle
jitter
Phase jitter
t_REFCJ
t_REFPJ
Min
Typical
Max Units
Comments
—
10 (8, 6.4)
—
ns 8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note: SGMII uses the 8 ns (125 MHz)
value only.
—
—
80
ps Difference in the period of any two
adjacent REFCLK cycles
–40
—
40
ps Deviation in edge location with respect to
mean edge location
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
41