MSC8144EC Datasheet, PDF (42/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
2.7.5.2 Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential
signals. Figure 12 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)
or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B.
TD or RD
A
B
TD or RD
Differential Peak-Peak = 2 × (A – B)
Figure 12. Differential V_PP of Transmitter or Receiver
Note: This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/
SRIO_RXD/SRIO_RXD respectively.
Using these waveforms, the definitions are as follows:
1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a peak-to-peak voltage
(V_PP) swing of A – B.
2. The differential output signal of the transmitter, V_OD, is defined as V_TD – V_TD.
3. The differential input signal of the receiver, V_ID, is defined as V_RD – V_RD.
4. The differential output signal of the transmitter and the differential input signal of the receiver each range from A – B
to –(A – B).
5. The peak value of the differential transmitter output signal and the differential receiver input signal is A – B.
6. The value of the differential transmitter output signal and the differential receiver input signal is 2 × (A – B) V_PP.
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common
mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5 V and 2.0 V. Using these values,
the peak-to-peak voltage swing of the signals TD and TD is 500 mV_PP. The differential output signal ranges between 500 mV
and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV_PP.
Note:
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud
rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI
electrical interface specified in Clause 47 of IEEE™ Std 802.3ae-2002™. XAUI has similar application goals to
serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for
XAUI, suitably modified for applications at the baud intervals and reaches described herein.
2.7.5.3 Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such
as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye
opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be
used. The most common equalization techniques that can be used are:
• A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.
• The use of active circuits in the receiver. This is often referred to as adaptive equalization.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
42
Freescale Semiconductor