MSC8144EC Datasheet, PDF (37/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
Table 23 summarizes the reset actions that occur as a result of the different reset sources.
Table 23. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)
External only
Configuration pins sampled (Refer to
Yes
Section 2.7.3.2 for details).
PLL state reset
Yes
Select reset configuration source
Yes
System reset configuration write
Yes
HRESET driven
Yes
IPBus modules reset (TDM, UART, SWT,
Yes
DDRC, IPBus master, GIC, HS, and GPIO)
SRESET driven
Yes
Extended cores reset
Yes
CLASS registers reset
Yes
Timers, Performance Monitor
Yes
Packet Processor, PCI, DMA
Yes
Hard Reset (HRESET)
External or Internal
(Software Watchdog,
Software or RapidIO)
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Soft Reset (SRESET)
External or
internal
Software
No
No
No
No
No
Yes
Yes
Yes
Some
registers
No
Most
registers
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
No
No
No
No
No
Yes
Depends on command
Yes
Some registers
No
Most registers
2.7.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 32 CLKIN cycles after
V_DD and V_DDIO are both at their nominal levels.
2.7.3.2 Reset Configuration
The MSC8144EC has two mechanisms for writing the reset configuration:
• Through the I²C port
• Through external pins
• Through internal hard coded
Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the
Reset Word Configuration Source and operating conditions:
• RCW_SRC[2–0]
• RC[16–0]
The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid
and is also sampled during power-on reset sequence for RCW loading from an I²C EEPROM.
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
37