MSC8144EC Datasheet, PDF (35/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
2.7.1 Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2
describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144EC device:
• PORESET and TRST must be asserted externally for the duration of the power-up sequence using the V_DDIO (3.3 V)
supply. See Table 24 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.
During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.
Note:
•
•
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
V_DDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
(see Figure 7). 32 cycles should be accounted only after V_DDIO reaches its nominal value.
CLKIN and PCI_CLK_IN should either be stable low during the power-up of V_DDIO supply and start their swings after
power-up or should swing within V_DDIO range during V_DDIO power-up., so their amplitude grows as V_DDIO grows
during power-up.
Figure 7 shows a sequence in which V_DDIO is raised after V_DD and CLKIN begins to toggle with the raise of V_DDIO supply.
V_DDIO = Nominal
V_DD = Nominal
3.3 V
1
V_DDIO Nominal
1.0 V
V_DD Nominal
PORESET/TRST asserted
V_DD applied
CLKIN starts toggling
V_DDIO applied
PORESET
Time
Figure 7. Start-Up Sequence with V_DD Raised Before V_DDIO with CLKIN Started with V_DDIO
2.7.2 Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 20 shows the maximum frequency values for
internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that
maximum frequency values are not exceeded.
Table 20. Clock Frequencies
CLKIN frequency
PCI_CLK_IN frequency
CLKIN duty cycle
PCI_CLK_IN duty cycle
Characteristic
Symbol
F_CLKIN
F_{PCI_CLK_IN}
D_CLKIN
D_{PCI_CLK_IN}
MIN
25
25
40
40
Max
150
150
60
60
Unit
MHz
MHz
%
%
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
35