MSC8144EC Datasheet, PDF (52/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

TDMxTCLK
TDMxTDAT
t_TDMCH
t_TDMC
t_TDMCL
t_TDMDHOV
t_TDMDHOX
t_TDMDHOZ
t_TDMHOX
TDMxTSYN
t_TDMSHOV
t_TDMSHOX
Figure 21. TDM Output Signals
Note: For some TDM modes transmit data is being output on other pins. This timing is valid for it as well. See the MSC8144EC
Reference Manual
2.7.8 UART Timing
Table 43. UART Timing
Characteristics
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
Note: T_UREFCLK = T_REFCLK is guaranteed by design.
Symbol
T_UREFCLK
T_UAVKH
T_UAVXH
Expression
16 × T_REFCLK
Figure 22 shows the UART input AC timing
T_UAVKH
T_UAVKH
UTXD, URXD
inputs
T_UREFCLK
T_UREFCLK
Figure 22. UART Input Timing
Figure 23 shows the UART output AC timing
Min
Max Unit
160
—
ns
6
ns
5.5
ns
UTXD output
T_UAVXH
T_UAVXH
Figure 23. UART Output Timing
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
52
Freescale Semiconductor