MSC8144EC Datasheet, PDF (51/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
2.7.7 TDM Timing
Table 42. TDM Timing
Characteristic
Symbol
Expression
Min
Max Units
TDMxRCLK/TDMxTCLK
TDMxRCLK/TDMxTCLK high pulse width
TDMxRCLK/TDMxTCLK low pulse width
TDM receive all input set-up time related to TDMxRCLK
TDMxTSYN input set-up time related to TDMxTCLK in TSO=0 mode
t_TDMC
TC¹
16
t_TDMCH
(0.5 ± 0.1) × TC⁴
7
t_TDMCL
(0.5 ± 0.1) × TC⁴
7
t_TDMVKH
3.6
—
ns
—
ns
—
ns
—
ns
TDM receive all input hold time related to TDMxRCLK
TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode
t_TDMXKH
1.9
—
ns
TDMxTCLK high to TDMxTDAT output active²
TDMxTCLK high to TDMxTDAT output valid²
All output hold time (except TDMxTSYN) ³
TDMxTCLK high to TDMxTDAT output high impedance²
TDMxTCLK high to TDMxTSYN output valid²
TDMxTSYN output hold time³
t_TDMDHOX
t_TDMDHOV
t_TDMHOX
t_TDMDHOZ
t_TDMSHOV
t_TDMSHOX
2.5
—
ns
—
9.8
ns
2.5
—
ns
—
9.8
ns
—
9.25
ns
2.0
—
ns
Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
2. Values are based on 20 pF capacitive load.
3. Values are based on 10 pF capacitive load.
4. The expression is for common calculations only.
Figure 19 shows the TDM input AC timing.
TDMxRCLK
t_TDMVKH
TDMxRDAT
t_TDMVKH
TDMxRSYN
t_TDMCH
t_TDMC
t_TDMCL
t_TDMXKH
t_TDMXKH
Figure 19. TDM Inputs Signals
Note: For some TDM modes receive data and receive sync are being input on other pins. This timing is valid for them as well.
See the MSC8144EC Reference Manual.
Figure 20 shows TDMxTSYN AC timing in TSO=0 mode.
TDMxTCLK
t_TDMVKH
TDMxTSYN
t_TDMXKH
Figure 20. TDMxTSYN in TSO=0 mode
Figure 21 shows the TDM Output AC timing
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
51