MSC8144EC Datasheet, PDF (36/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
Table 21. Clock Parameters
Characteristic
Min
CLKIN slew rate (20%-80%)
1
PCI_CLK_IN slew rate (20%-80%)
1
Max
—
—
Unit
V/ns
V/ns
2.7.3 Reset Timing
The MSC8144EC has several inputs to the reset logic:
• Power-on reset (PORESET)
• External hard reset (HRESET)
• External soft reset (SRESET)
• Software watchdog reset
• JTAG reset
• RapidIO reset
• Software hard reset
• Software soft reset
All MSC8144EC reset sources are fed into the reset controller, which takes different actions depending on the source of the
reset. The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources.
Table 22. Reset Sources
Name
Power-on reset
(PORESET)
External hard
reset (HRESET)
External soft reset
(SRESET)
Host reset
command through
the TAP
Software
watchdog reset
RapidIO reset
Software hard
reset
Software soft reset
Direction
Input
Input/ Output
Input/ Output
Internal
Internal
Internal
Internal
Internal
Description
Initiates the power-on reset flow that resets the MSC8144EC and configures various attributes of the
MSC8144EC. On PORESET, the entire MSC8144EC device is reset. All PLLs states is reset,
HRESET and SRESET are driven, the extended cores are reset, and system configuration is
sampled. The reset source and word are configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC8144EC. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that
the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on
reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144EC
Reference Manual.
Initiates the soft reset flow. The MSC8144EC detects an external assertion of SRESET only if it
occurs while the MSC8144EC is not asserting reset. SRESET is an open-drain pin. Upon soft reset,
SRESET is driven, the extended cores are reset, and system configuration is maintained.
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
When the MSC8144EC watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset
sequence.
A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
36
Freescale Semiconductor