MSC8144EC Datasheet, PDF (62/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

2.7.14 JTAG Signals
Table 55. JTAG Timing
Characteristics
Symbol
TCK cycle time
t_TCKX
TCK clock high phase measured at V_M = 1.6 V
t_TCKH
TCK rise and fall times
t_TCKR
Boundary scan input data set-up time
t_BSVKH
Boundary scan input data hold time
t_BSXKH
TCK fall to output data valid
t_TCKHOV
TCK fall to output high impedance
t_TCKHOZ
TMS, TDI data set-up time
t_TDIVKH
TMS, TDI data hold time
t_TDIXKH
TCK fall to TDO data valid
t_TDOHOV
TCK fall to TDO high impedance
t_TDOHOZ
TRST assert time
t_TRST
Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.
All frequencies
Min
Max
36.0
—
15.0
—
—
3.0
0.0
—
15.0
—
—
20.0
—
24.0
0.0
—
5.0
—
—
10.0
—
12.0
100.0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 40 Shows the Test Clock Input Timing Diagram
t_TCKX
TCK
V_M
(Input)
t_TCKR
t_TCKH
V_M
t_TCKR
Figure 39. Test Clock Input Timing
Figure 41 Shows the boundary scan (JTAG) timing diagram.
TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
t_TCKHOV
t_TCKHOZ
t_BSVKH
t_BSXKH
Input Data Valid
Output Data Valid
Figure 40. Boundary Scan (JTAG) Timing
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
62
Freescale Semiconductor