MSC8144EC Datasheet, PDF (49/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Electrical Characteristics
2.7.5.9 Jitter Test Measurements
For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (baud frequency)/1667 is
applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in
Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and
opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.
Single lane implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be
measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance
setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE Std.
802.3ae.
2.7.5.10 Transmit Jitter
Transmit jitter is measured at the driver output when terminated into a load of 100 Ω resistive ±5% differential to 2.5 GHz.
2.7.5.11 Jitter Tolerance
Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum
of deterministic and random jitter defined in Section 2.7.5.9 and then adjusting the signal amplitude until the data eye contacts
the 6 points of the minimum eye opening of the receive template shown in Figure 15 and Table 40. Note that for this to occur,
the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)
about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using
a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter
specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.
2.7.6 PCI Timing
This section describes the general AC timing parameters of the PCI bus. Table 41 provides the PCI AC timing specifications.
Table 41. PCI AC Timing Specifications
Parameter
33 MHz
66 MHz
Symbol
Unit
Min
Max
Min
Max
Output delay
t_PCVAL
2.0
11.0
1.0
6.0
ns
High-Z to Valid Output delay
t_PCON
2.0
—
1.0
—
ns
Valid to High-Z Output delay
t_PCOFF
—
28
—
14
ns
Input setup
t_PCSU
7.0
—
3.0
—
ns
Input hold
t_PCH
0
—
0
—
ns
Reset active time after PCI_CLK_IN stable
t_PCRST-CLK
100
—
100
—
μs
Reset active to output float delay
t_PCRST-OFF
—
40
—
40
ns
Reset active time after power stable
t_PCRST
1
—
1
—
ms
HRESET high to first Configuration Access
t_PCRHFA
32M
—
32M
—
clocks
Notes: 1. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
2. All PCI signals are measured from 0.5 × V_DDIO of the rising edge of PCI_CLK_IN to 0.4 × V_DDIO of the signal in question for
3.3-V PCI signaling levels.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The reset assertion timing requirement for HRESET is in Table 24 and Figure 8
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
49