MSC8144EC Datasheet, PDF (55/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Table 47. MII Receive AC Timing Specifications (continued)
Parameter/Condition
Symbol ¹
Min
Max
Unit
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
t_MRDVKH
10.0
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
t_MRDXKH
2
—
ns
RX_CLK clock rise
t_MRXR
1.0
4.0
ns
RX_CLK clock fall time
t_MRXF
1.0
4.0
ns
Notes: 1. Typical RX_CLK period (t_MRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.
2. Program GCR4 as 0x00030CC3.
Figure 27 provides the AC test load.
Output
Z₀ = 50 Ω
R_L = 50 Ω
V_DDGE/2
Figure 27. AC Test Load
Figure 28 shows the MII receive AC timing diagram.
RX_CLK
RXD[3:0]
RX_DV
RX_ER
t_MRX
t_MRXR
t_MRXH
t_MRXF
Valid Data
t_MRDVKH
t_MRDXKH
Figure 28. MII Receive AC Timing
2.7.10.4 RMII Transmit and Receive AC Timing Specifications
Table 48 provides the RMII transmit and receive AC timing specifications.
Table 48. RMII Transmit and Receive AC Timing Specifications
Parameter/Condition
REF_CLK duty cycle
REF_CLK to RMII data TXD[1–0], TX_EN delay
RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK
RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK
REF_CLK data clock rise
REF_CLK data clock fall
Typical REF_CLK clock period (t_RMX) is 20 ns
Notes: 1. Typical REF_CLK clock period (t_RMX) is 20 ns
2. Program GCR4 as 0x00001405
Symbol ¹
Min
t_RMXH/t_RMX
35
t_RMTKHDX
2
t_RMRDVKH
4.0
t_RMRDXKH
2.0
t_RMXR
1.0
t_RMXF
1.0
Max
65
10
—
—
4.0
4.0
Unit
%
ns
ns
ns
ns
ns
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
55