MSC8144EC Datasheet, PDF (72/80 Pages) Freescale Semiconductor, Inc – Quad Core Digital Signal Processor

Hardware Design Considerations
Table 65. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)
Signal Name
Pin Connection
GE2_SGMII_RX
GE2_SGMII_TX
GE2_SGMII_TX
GE2_TCK
GE2_TD[0–3]
GE2_TX_EN
GND_SXC
NC
NC
NC
NC
NC
3.4.4.3 GE1 and GE2 Management Pins
GE_MDC and GE_MDIO pins should be connected as required by the specified protocol. If neither GE1 nor GE2 is used (that
is, V_DDGE2 is connected to GND), Table 67 lists the recommended management pin connections.
Table 66. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used
Signal Name
Pin Connection
GE_MDC
NC
GE_MDIO
NC
3.4.5 UTOPIA/POS Related Pins
Table 68 lists the board connections of the UTOPIA/POS pins when the entire UTOPIA/POS interface is not used or subset of
UTOPIA/POS interface is used. For multiplexing options that select a subset of the UTOPIA/POS interface, use the connections
described in Table 68 for those signals that are not selected. Table 68 assumes that the alternate function of the specified pin is
not used. If the alternate function is used, connect that pin as required to support the selected function.
Table 67. Connectivity of UTOPIA/POS Related Pins When UTOPIAPOS Interface Is Not Used
UTP_IR
UTP_RADDR[0–4]
UTP_RCLAV_PDRPA
UTP_RCLK
UTP_RD[0–15]
UTP_REN
UTP_RPRTY
UTP_RSOC
UTP_TADDR[0–4]
UTP_TCLAV
UTP_TCLK
UTP_TD[0–15]
UTP_TEN
UTP_TPRTY
Signal Name
Pin Connection
GND
V_DDIO
NC
GND
GND
V_DDIO
GND
GND
V_DDIO
NC
GND
NC
V_DDIO
NC
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
72
Freescale Semiconductor